Education:

• Ph.D (Pursuing) in Low Power VLSI Design, J.N.T. University, Hyderabad. under the guidance of Dr. B K Madhavi and Dr. K Lal Kishore. Planning to submit the Ph.D Thesis in March 2012.
• M.Tech., Communication Systems with distinction, from SV University, Tirupati.
• B.Tech., Electronics and Communication Engineering with Distinction, from G Pulla Reddy Engineering College, Kurnool.

Work Experience:  9 Years

Courses Taught:

• Electric Circuits/Network Analysis
• VLSI Design
• Microprocessors and Interfacing
• Pulse and Digital Circuits
• Analog Communications
• Digital IC Applications
• Electronic Circuit Analysis
• TV Engineering
• Digital Logic Design
• STLD
• EDC 

Journals and Conferences:

• Rajendra Prasad S, Dr. B K Madhavi and Dr. K Lal Kishore, “A New Lo-Power 9T SRAM Cell based on CNTFET at 32nm Technology Node”, International Journal of Computer Science and Information Technologies (IJCSIT), Nov-Dec, 2011.
• Rajendra Prasad S, Dr. B K Madhavi and Dr. K Lal Kishore, “High-Performance Memory Cell Design at 32nm Technology based on CNTFET for Low-Power Embedded Systems”, International Journal of Advances in Science and Technology (IJAST), October, 2011.
• Rajendra Prasad S, Dr. B K Madhavi, and Dr. K. Lal Kishore and Rangaiah L, “Reduction of Delay and Cross Talk using Buffer Insertion Method”, International Journal of Electrical, Electronics and  Computing Technology (IJEECT),  January-April 2011.
• Rajendra Prasad S and Dr. B K Madhavi, “Efficient Low Power Designs for Embedded systems”, National Conference on Nanoelectronics, Vaagdevi College of Engineering, Warangal, on 25th December, 2007.
• Rangaiah, L., Srinivasa Rao, K., Krishna, NVM., Rajendra Prasad, S & Srinivasa Rao, D, “Conceptual and Optimization Problems in Wireless Ad-hoc Sensor Networks”, International Journal of Electrical, Electronics and Computing Technology (IJEECT), September-December 2010.

Workshops Conducted:

• As a Coordinator conducted a 3-day National level Workshop on Analog and Digital VLSI Circuits Design Using CADENCE Tools, from 27th-29th June 2011, organized by the department of ECE, ACE Engineering College, Hyderabad.

Workshops & Conferences Attended:

• 3-day National level Workshop on “Analog and Digital VLSI Circuits Design Using CADENCE Tools”, from 27th-29th June 2011, Organized by the department of ECE, ACE Engineering College, Hyderabad.
• 5-day Workshop on “VLSI Design Methodology using Mentor Graphics tools”, jointly organized by JNTU, Mentor Graphics Corp., & Trident Techlabs, held on 9th -13th August, 2010 at Hyderabad.
• 3-day Workshop on “Advances in Communication Techniques & Technologies”, organized by School of Electronics, Sreenidhi Institute of Science and Technology, Ghatkesar, Hyderabad, from July 8-10, 2010.
• One-day Workshop on “VLSI Circuits and Layout Simulation using ECAD Tools”, organized by School of Electronics, Sreenidhi Institute of Science and Technology, Ghatkesar, Hyderabad on April 17, 2010.
• 2-day Workshop on “Low Power VLSI Design Methodologies”, held on 11th and 12th of December, 2009, jointly organized by Synopsys (India) pvt. Ltd., Hyderabad and CVED, JNTUH.
  The 21st International Conference on “VLSI Design”, organized by VEDA IIT Hyderabad, held at Hyderabad, from 4th -8th Jnauary, 2008.
• National Symposium on “Nanoelectronics”, Organized by the Department of ECE & EIE, Vaagdevi College of Engineering, Warangal, on 25th December, 2007.